1997 DIRECTOR�S DISCRETIONARY FUND ANNUAL REPORT

TITLE: Advanced Integrated Circuit Shielding Techniques

LEADER: Ann Garrison-Darrin, 310

OTHER IN-HOUSE TEAM MEMBERS: Richard Katz, 738, Dr. Henning Leidecker, 311

COLLABORATORS: Jeanette Plante, Swales Aerospace, Dr. Mark Fan, Swales Aerospace, Lance LeBeau, Jackson and Tull, Glen Davis, Jackson and Tull.

PURPOSE OF THE INVESTIGATION: Spot radiation shielding has been an approach for protecting insufficiently radiation hardened circuitry which must be used in space. When bought through packaging houses these shields do not always provide sufficient protection to the IC and increased costs are introduced in a number of ways. The packaging house must buy dice from the IC manufacturer and is responsible for full qualification of the final part. The cost of fixturing and running these tests and the long lead times associated with procuring bare dice can have negative effects on NASA project budgets and schedules. Experience has shown inadequate testing of these devices, only marginal shielding effectiveness and a five fold increase in cost. This situation is exacerbated when complex devices, such as field programmable gate arrays, are needed.

This task was proposed to investigate spot shielding of off-the-shelf, high reliability IC�s to avoid cost and schedule burdens inherent in third party packaging approaches. The Actel 1280 family of field programmable gate arrays (FPGA�s), in 172 pin quad flat-packs, was chosen as the technology vehicle due to its complexity and wide ranging applicability throughout NASA programs. This work intended to establish an approach, including material procurement and package processing by NASA, that will make radiation shielding of packaged parts fairly straightforward and low in cost. This is especially useful for the more complex, fine pitched packages, such as the 172, 196 and 257 pin ceramic quad flatpacks (CQFP172, CQFP196 and CQFP257).

INITIATION: FY96

FY96 AUTHORIZED FUNDING: $ 40

FY97 AUTHORIZED FUNDING: $ 16

FY97 EXPENDITURES: $18 K on the design and fabrication of the test boards and fixturing, vibration testing, and empirical and theoretical analysis of the results of the first test.

STATUS AT END OF FY97: No funds remaining.

Boards were fabricated with four Actel gate arrays in ceramic, 172 lead flat pack packages. Tungsten Copper shields, 0.200" thick were epoxied under and on top of each of the four devices. An especially deep lead bend was designed and applied to allow the solder connection of the leads. Testing was run in accordance with MIL-STD-883, Method 2026, Condition I-A through I-H (11.6 Grms through 36.6 Gs) for vibration and 100 Gpeak, 1ms pulse, 5x in each (X1 and X2) direction for shock. The shock test was performed after the first vibration test (11.9 Grms) and was followed by more vibration testing at 16.4 Grms. One out of four parts� leads were broken after the 16.4Grms test. (Figure 1). Inspection revealed that this was probably due to a failure of the epoxy at the

Figure 1. Broken leads due to failure of epoxy interface

shield to board interface since the remaining four parts did not have a failed epoxy joint and did not have any broken leads. There was concern, based on a resonance found at 1 kHz, that board flexure may have contributed to the failure (Figure 2). A finite element analysis was performed for the board, the tungsten copper shields and the epoxy to determine at which frequencies the resonant modes were being excited. An assessment of that analysis has not been completed however some modal shapes from the exercise are shown here (Figure 3).

Figure 2. Response of a monitored part with vibration in the X direction

A second board has been designed, fabricated and validated electrically to use in a second round of testing. Thinner, lighter shields will be used (The 0.200" thickness represents a manufacturing limit. Thinner shields will more likely be applied considering the shielding effectiveness of the material) and leads will be daisy chained to allow active monitoring during the test. The test procedure has been modified for this second test however the testing has not been performed.

Figure 3. Finite Element Analysis Models of Populated Test Board

PLANNED FUTURE WORK: Funding has not been sought from the DDF process to fund continuation of this project however the intention is to complete the second round of tests to validate the viability of spot radiation shielding in this manner.