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Implementation of a Multichannel Serial Data Streaming Algorithm using the Xilinx Serial RapidIO SolutionIn the current world of applications that use reconfigurable technology implemented on field programmable gate arrays (FPGAs), there is a need for flexible architectures that can grow as the systems evolve. A project has limited resources and a fixed set of requirements that development efforts are tasked to meet. Designers must develop robust solutions that practically meet the current customer demands and also have the ability to grow for future performance. This paper describes the development of a high speed serial data streaming algorithm that allows for transmission of multiple data channels over a single serial link. The technique has the ability to change to meet new applications developed for future design considerations. This approach uses the Xilinx Serial RapidIO LOGICORE Solution to implement a flexible infrastructure to meet the current project requirements with the ability to adapt future system designs.
Document ID
20160010558
Acquisition Source
Glenn Research Center
Document Type
Technical Memorandum (TM)
Authors
Doxley, Charles A.
(NASA Glenn Research Center Cleveland, OH United States)
Date Acquired
August 24, 2016
Publication Date
August 1, 2016
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NASA/TM-2016-219117
E-19241
GRC-E-DAA-TN18291
Funding Number(s)
WBS: WBS 289972.02.07.02.02
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Keywords
RapidIO
High Speed Data
Serial Backplane
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