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Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantationThe procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.
Document ID
19840021018
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Woo, D. S. (RCA Solid State Technology Center Somerville, NJ, United States)
Date Acquired
September 4, 2013
Publication Date
January 1, 1982
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
RCA-PRRL-81-CR-19
NASA-CR-161988
NAS 1.26:161988
Accession Number
84N29087
Funding Number(s)
CONTRACT_GRANT: NAS8-31986
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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